The Quiet Race: Intel’s Big Bet on Advanced Packaging to Grab a Slice of the AI Boom
Roughly 16 miles outside Albuquerque, New Mexico, on a 200+ acre plot in the city of Rio Rancho, sits one of Intel’s oldest chip manufacturing campuses. The site first opened in the 1980s, with portions of its facility built over what was once a commercial sod farm. When Intel’s business hit a major slump in 2007, core production at one of its key fabs here, Fab 9, was permanently halted. In the years after the shutdown, former employees say families of raccoons and even a badger ended up making the idle factory floor their new home.
That all changed in January 2024, when the long-dormant fab powered back on. Intel poured billions of dollars into modernizing the facility, including $500 million in public funding secured through the U.S. CHIPS and Science Act. Today, Fab 9 and its adjacent on-site counterpart, Fab 11X, form the backbone of one of Intel’s fastest-growing, under-the-radar business lines: advanced semiconductor packaging.
Advanced packaging is the process of combining dozens of smaller individual components, called chiplets, into a single custom-built semiconductor. Over the past six months, Intel has repeatedly signaled that its advanced packaging segment, which operates under the company’s Intel Foundry contract manufacturing division, is experiencing an explosive growth spurt. The push puts Intel in direct competition with Taiwan Semiconductor Manufacturing Company (TSMC), the global leader in chip manufacturing that dwarfs Intel’s current production output by volume. But in an era where artificial intelligence is spurring unprecedented demand for all types of computing power, and pushing nearly every major tech firm to design their own custom in-house chips, Intel executives believe packaging can help the company capture a larger share of the booming AI market.
During Intel’s quarterly earnings call in January, CEO Lip-Bu Tan framed the company’s packaging capabilities as a “very big differentiator” that sets Intel apart from rival contract manufacturers. CFO Dave Zinsner added on the same call that revenue from packaging services will hit the company’s books “even before we start to see meaningful wafer revenue.” Over the prior 12 to 18 months, Zinsner noted, he had upwardly revised his packaging revenue projections from hundreds of millions of dollars annually to “well north of $1 billion.”
Zinsner expanded on that outlook at the Morgan Stanley Technology, Media & Telecom Conference in March, calling Intel’s packaging segment “ironically, the more interesting part of the Foundry business today.” He added that the company is “close to closing some deals that are in the billions of dollars per year, in terms of revenue on packaging.”
Multiple industry sources familiar with the discussions tell WIRED that Intel has held ongoing talks with at least two major potential clients for its advanced packaging services: Google and Amazon. Both companies design their own custom AI and server chips, but outsource portions of their manufacturing and assembly processes. Securing deals with either giant would be a major win for Intel, which has struggled with years of stagnation and missed opportunities in the mobile chip market, and is currently attempting a large-scale comeback partially funded by U.S. government subsidies.
Spokespeople for Google and Amazon both declined to comment for this story, with Google noting it does not publicly discuss relationships with its suppliers, and Intel also declined to comment on any specific customer discussions.
Intel’s Foundry Split and the Stakes for Packaging
Intel’s ambitions for its advanced packaging business hinge almost entirely on securing outside clients like these tech giants. Starting in 2024, the company effectively split its operations into two distinct divisions: the long-established product side, which designs and sells energy-efficient CPUs to PC makers and data center operators, and the newer, growth-focused Intel Foundry division, which manufactures advanced semiconductors for external clients.
Intel Foundry’s progress, including its packaging capacity and output, is closely watched by analysts and investors, who have watched the company cycle through multiple CEOs and repeatedly pause and restart major fab construction projects over the past decade. For his part, Zinsner said at the Morgan Stanley conference that he expects Intel Foundry’s packaging business to hit the same 40% gross margin target that the company targets for the rest of its product lines.
Even so, turning that ambitious outlook into reality remains an enormous challenge. “Packaging is not as easy as saying ‘I want to run 100,000 wafers per month,’” says Jim McGregor, a veteran semiconductor analyst and founder of Tirias Research, referring to the steady, high-volume output required for profitable chip manufacturing. “It really comes down to whether Intel’s [packaging] fabs can lock in deals. If we see them expanding those operations more, that’s an indicator that they have.”
Just last month, Malaysian Prime Minister Anwar Ibrahim announced in a Facebook post that Intel is moving forward with an expansion of its chip manufacturing facilities in the country, which first opened in the 1970s. Ibrahim wrote that Intel Foundry head Naga Chandrasekaran had “outlined plans to commence the first phase” of the expansion project, which will include new advanced packaging capacity. A translated version of the post reads: “I welcome Intel's decision to begin operations for the complex later this year.” Intel spokesperson John Hipsher confirmed the project, saying the company is building out additional chip assembly and test capacity in Penang “amid rising global demand for Intel Foundry packaging solutions.”
How Advanced Packaging Became an AI Priority
In an exclusive interview with WIRED for this story, Chandrasekaran, who took over leadership of Intel Foundry in 2025, notes that the term “advanced packaging” didn’t even exist a decade ago.
All chips require some level of integration of core components like transistors and capacitors, which control and store electrical energy. For decades, the global semiconductor industry was almost entirely focused on miniaturization: shrinking the size of individual components on a single silicon wafer. By the 2010s, as consumer and enterprise devices demanded more and more computing power, chips became far denser, packing more processing cores, high-bandwidth memory, and connecting components into the same physical footprint. Eventually, chipmakers shifted to modular approaches like system-in-package and package-on-package design, which stack multiple small components on top of one another to squeeze more processing power and memory into the same amount of surface space. What started as 2D stacking quickly evolved into more complex 3D stacking techniques.
TSMC, the world’s largest contract chip manufacturer, was an early mover in the space, rolling out packaging technologies like CoWoS (chip on wafer on substrate) and later SoIC (system on integrated chip) for its clients. TSMC’s value proposition was simple: it would handle not just the “front end” of chip manufacturing (producing the raw silicon wafers) but also the “back end” work of assembling and packaging all components into a finished chip.
Intel had already lost its position as the global leader in cutting-edge chip manufacturing to TSMC by this point, but it continued to pour research and development funding into its own packaging technology. In 2017, the company launched EMIB, or embedded multi-die interconnect bridge, a unique process that shrinks the physical connections (or bridges) between individual components in a packaged chip. Two years later, it introduced Foveros, an advanced 3D die-stacking process. Its next major advancement, EMIB-T, represented a far larger leap forward.
Announced this past May, EMIB-T is designed to boost power efficiency and improve signal integrity between all components on a finished chip. One former Intel employee with direct knowledge of the company’s packaging work tells WIRED that Intel’s EMIB and EMIB-T platforms are engineered to be a more “surgical” approach to chip packaging than TSMC’s competing methods. Like most advancements in semiconductors, this translates to better power efficiency, smaller overall chip sizes, and ideally lower long-term costs for customers. Intel says EMIB-T will launch in commercial fabs later this year.
Unsurprisingly, the AI boom has been the biggest catalyst for the sudden growth of advanced packaging. “Because of AI, advanced packaging has really come to the forefront,” Chandrasekaran said. “Even more so than the silicon itself, chip packaging is going to transform how this AI revolution comes to fruition over the next decade.”
Intel has based its EMIB-T mass production preparations right here in Rio Rancho. The facility currently employs roughly 2,700 Intel workers, around 200 fewer than it had last year, after CEO Tan implemented widespread layoffs across the company shortly after taking the top role. The site sits surrounded by arid desert, and like many large tech infrastructure expansions, local advocacy groups have raised serious concerns about the facility’s water consumption and air emissions. (Intel says it recycles water at the Rio Rancho site.)
A quick walk through Fab 9 reveals little out of the ordinary to an untrained visitor. It is slightly less sterile than Intel’s cutting-edge Fab 52 in Arizona, due to a different air particle filtration system, but standard clean room protocols—including full-body sanitized hazmat suits—are still required to enter. Inside the fab, hair-thin silicon wafers are mounted, diced, and ground-molded into finished packaged chips.
During a tour of the facility, Katie Prouty, Rio Rancho’s site plant manager and a 31-year Intel veteran, highlighted that one of Intel’s biggest selling points for advanced packaging is its flexibility for clients: customers can choose to work with Intel for any single step of the production process, or “enter and exit the highway” at any point. For example, a customer can source silicon wafers from another manufacturer, then bring them to Intel’s fabs for packaging; or they can get basic traditional packaging from an outsourced semiconductor assembly and test (OSAT) provider, then turn to Intel for the advanced packaging step.
“That’s not something Intel did before. We never took in other customers’ wafers,” Prouty said. “That’s been a huge mindset shift.”
Where Are the Customers?
So Intel checks all the boxes: competent cutting-edge technology, packaging purpose-built for AI chips, flexible terms that work for clients with existing supply chains. So where are all the confirmed customers?
One former Intel employee, who spoke on condition of anonymity, says potential target customers are hesitant to publicly announce partnerships with Intel for two key reasons. Many are still waiting to confirm that Intel can deliver on its fab expansion promises, and others fear that TSMC could reduce wafer allocations to their company if they publicly disclose they’re working with Intel on packaging. The risk isn’t with Intel’s packaging technology itself, the former employee added—it’s with broader market dynamics and existing supply chain relationships.
Chandrasekaran takes a more measured approach, noting that Intel’s policy is to not discuss specific clients. “I think we want to be very disciplined around the idea of: We don’t talk about our customers,” he said. “Successful foundries don’t say, ‘We have signed up these customers.’ We want the customers to talk about our product.”
It might be fair to update the old “Field of Dreams” motto for Intel: if the customers come, Intel will build out the capacity—at no small capital cost. Chandrasekaran says the clearest public sign that customers have signed on will be a noticeable jump in Intel Foundry’s capital spending. “As we sign up these customers, we’ll have to increase our capital expenditures,” he says. “And then the street will see it.”
